1. Field of the Invention
Embodiments of the present invention generally relate to the field of semiconductor manufacturing. More specifically, the present invention relates to a method of forming a silicon oxynitride (SiOxNy) gate dielectric and integrating it into a gate stack using plasma nitridation and a two-step post plasma nitridation annealing (PNA) process.
2. Description of the Related Art
Integrated circuits are made up of literally millions of active and passive devices that function as basic components such as transistors, capacitors and resistors. A transistor generally includes a source, a drain, and a gate stack. The gate stack consists of the substrate (silicon) on top of which is grown a dielectric (usually silicon dioxide: SiO2) and this is capped with an electrode (such as polycrystalline silicon).
As integrated circuit sizes and the sizes of the transistors thereon decrease, the gate drive current required to increase the speed of the transistor has increased. Because the drive current increases as the gate capacitance increases, and capacitance is inversely proportional to the gate dielectric thickness, decreasing the dielectric thickness is one method of increasing the drive current.
Attempts have been made to reduce the thickness of SiO2 gate dielectrics below 20 Å. However, it has been found that the use of thin SiO2 gate dielectrics below 20 Å often results in undesirable effects on gate performance and durability. For example, boron from a boron doped gate electrode can penetrate through a thin SiO2 gate dielectric into the underlying silicon substrate. Also, there is typically an increase in gate leakage, i.e., tunneling, with thin dielectrics that increases the amount of power consumed by the gate. Thin SiO2 gate dielectrics may be susceptible to hot carrier damage, in which high energy carriers traveling across the dielectric can damage or destroy the gate. Thin SiO2 gate dielectrics may also be susceptible to negative bias temperature instability (NBTI), wherein the threshold voltage or drive current drifts with operation of the gate.
Consequently, there is a need for an alternative gate dielectric material that can be used in a large enough physical thickness to reduce current leakage density and still provide a high gate capacitance. In order to achieve this, the alternative gate dielectric material must have a dielectric constant that is higher than that of silicon dioxide. Typically, the thickness of such an alternative dielectric material layer is expressed in terms of the equivalent oxide thickness (EOT). Thus, the EOT of an alternative dielectric layer in a particular capacitor is the thickness that the alternative dielectric layer would have if its dielectric constant were that of silicon dioxide.
One method that has been used to address the problems with thin SiO2 gate dielectrics is to incorporate nitrogen into the SiO2 layer to form a SiOxNy gate dielectric. Incorporating nitrogen into the SiO2 layer blocks boron penetration into the underlying silicon substrate and raises the dielectric constant of the gate dielectric, allowing the use of a thicker dielectric layer.
Thermally grown silicon oxynitride has been used as gate dielectrics for several years from the 0.2 μm to 0.13 μm device generations. As the device technology has advanced from 0.2 μm to 0.1 μm the gate oxide has thinned from >25 Å to <12 Å. In order to block boron and reduce gate leakage the amount of nitrogen in the film has been increased from <3% for 25 Å SiOxNy layers to 5-10% for 12 Å SiOxNy layers. When nitric oxide (NO) and nitrous oxide (N2O) are used to grow the oxynitride gate dielectric the nitrogen gets incorporated in the dielectric film simultaneously as the oxynitride grows, hence nitrogen is distributed evenly in the film. If NO or N2O are used to form silicon oxynitride by annealing an existing SiO2 layer at elevated temperatures, the nitrogen is incorporated by growing SiON at the Si-substrate/Oxide interface. The amount of Nitrogen in the latter case (<2%) is less than in the former case (4-5%).
More recently, plasma nitridation (PN) has been used to nitride (to incorporate nitrogen into) the gate oxide. This technique results in high nitrogen concentration at the poly gate/oxide interface, which prevents boron penetration into the oxide dielectric. At the same time, the bulk of the oxide dielectric gets lightly doped with unassociated nitrogen during the plasma nitridation process, which reduces the electrical oxide thickness (EOT) over the starting oxide. This allows one to achieve a gate leakage reduction at the same EOT higher than conventional thermal processes. Scaling this dielectric in the EOT <12 Å range while preserving good channel mobility and drive current (Idsat) has been the industry challenge.
Post Nitridation Annealing (PNA) of the silicon oxynitride at high temperature has been shown as a method of improving the peak transconductance as a proxy for channel mobility, at the expense of the EOT increasing. These results are demonstrated in U.S. Patent Application Publication No. 2004/0175961, filed on Mar. 4, 2004, entitled “Two-Step Post Nitridation Annealing For Lower EOT Plasma Nitrided Gate Dielectrics,” assigned to Applied Materials, Inc., which is herein incorporated by reference to the extent it does not conflict with this application.
At low pressure and high temperature, SiO2 will breakdown into SiO which desorbs from the silicon surface resulting in a phenomenon called pitting.
Thus, there remains a need for an improved post anneal method for depositing a silicon oxynitride gate dielectric that has thinner EOT's with improved mobility while accounting for the problem of silicon monoxide desorption.